Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit

• Main Authors: Tan, Yung Sern, Yeo, Kiat Seng, Boon, Chirn Chye, Do, Manh Anh
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/99816; http://hdl.handle.net/10220/17712
• Institution: Nanyang Technological University

In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm will leads to a longer lock time for phase tracking loop and small ppm will leads to more switching time between the loops. A novel lock detector with hysteresis property is proposed in this paper. It provides two different ppms in both different conditions; a smaller ppm for in-lock condition and a larger ppm for out-of-lock condition. This paper also provides a detailed analysis of the proposed lock detector at different conditions. The proposed lock detector is simulated in 0.18- um technology and it consumes 1.1-mW at a 1.8V supply voltage.