Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs

10.1109/TED.2019.2904313

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Main Author:	THEAN VOON YEW, AARON
Other Authors:	ELECTRICAL AND COMPUTER ENGINEERING
Format:	Article
Published:	Institute of Electrical and Electronics Engineers Inc. 2020
Online Access:	https://scholarbank.nus.edu.sg/handle/10635/184240
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Institution:	National University of Singapore

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spelling	sg-nus-scholar.10635-1842402024-04-25T03:31:16Z Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs THEAN VOON YEW, AARON ELECTRICAL AND COMPUTER ENGINEERING 10.1109/TED.2019.2904313 IEEE Transactions on Electron Devices 66 5 2068 2020-11-30T02:44:47Z 2020-11-30T02:44:47Z 2019 Article THEAN VOON YEW, AARON (2019). Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs. IEEE Transactions on Electron Devices 66 (5) : 2068. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2019.2904313 00189383 https://scholarbank.nus.edu.sg/handle/10635/184240 Institute of Electrical and Electronics Engineers Inc.
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
description	10.1109/TED.2019.2904313
author2	ELECTRICAL AND COMPUTER ENGINEERING
author_facet	ELECTRICAL AND COMPUTER ENGINEERING THEAN VOON YEW, AARON
format	Article
author	THEAN VOON YEW, AARON
spellingShingle	THEAN VOON YEW, AARON Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs
author_sort	THEAN VOON YEW, AARON
title	Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs
title_short	Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs
title_full	Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs
title_fullStr	Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs
title_full_unstemmed	Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs
title_sort	highly scaled strained silicon-on-insulator technology for the 5g era: impact of geometry and annealing on strain retention and device performance of nmosfets
publisher	Institute of Electrical and Electronics Engineers Inc.
publishDate	2020
url	https://scholarbank.nus.edu.sg/handle/10635/184240
_version_	1800914446384627712

Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs

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