Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack

10.1116/1.2198849

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Bibliographic Details
Main Authors:	Joo, M.S., Park, C.S., Cho, B.J., Balasubramanian, N., Kwong, D.-L.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Article
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/56367
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-56367
record_format	dspace
spelling	sg-nus-scholar.10635-563672023-10-26T07:15:03Z Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack Joo, M.S. Park, C.S. Cho, B.J. Balasubramanian, N. Kwong, D.-L. ELECTRICAL & COMPUTER ENGINEERING 10.1116/1.2198849 Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures 24 3 1341-1343 JVTBD 2014-06-17T02:53:47Z 2014-06-17T02:53:47Z 2006-05 Article Joo, M.S., Park, C.S., Cho, B.J., Balasubramanian, N., Kwong, D.-L. (2006-05). Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures 24 (3) : 1341-1343. ScholarBank@NUS Repository. https://doi.org/10.1116/1.2198849 10711023 http://scholarbank.nus.edu.sg/handle/10635/56367 000238790000045 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
description	10.1116/1.2198849
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Joo, M.S. Park, C.S. Cho, B.J. Balasubramanian, N. Kwong, D.-L.
format	Article
author	Joo, M.S. Park, C.S. Cho, B.J. Balasubramanian, N. Kwong, D.-L.
spellingShingle	Joo, M.S. Park, C.S. Cho, B.J. Balasubramanian, N. Kwong, D.-L. Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
author_sort	Joo, M.S.
title	Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
title_short	Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
title_full	Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
title_fullStr	Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
title_full_unstemmed	Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
title_sort	interface configuration and fermi-level pinning of fully silicided gate and high-k dielectric stack
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/56367
_version_	1781781161523019776

Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack

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