Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack

Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack

10.1116/1.2198849

Saved in:
Bibliographic Details
Main Authors: Joo, M.S., Park, C.S., Cho, B.J., Balasubramanian, N., Kwong, D.-L.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Article
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/56367
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: National University of Singapore

Internet

http://scholarbank.nus.edu.sg/handle/10635/56367

Similar Items