A memory-efficient scalable architecture for lifting-based discrete wavelet transform
In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory efficiency and short critical path. The memory efficiency is achieved with a novel scanning method that enables tradeoff of external memory bandwidth and on-chip memory. Based on the data flow graph of the f...
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| Main Authors: | , |
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| 格式: | Article |
| 語言: | English |
| 出版: |
2013
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/102401 http://hdl.handle.net/10220/16815 |
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