Modeling, fabrication, and characterization of 3-D capacitor embedded in through-silicon via

• Main Authors: Lin, Ye, Tan, Chuan Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering; Capacitance Density; Integrated Capacitors
• Online Access: https://hdl.handle.net/10356/140157
• Institution: Nanyang Technological University

A new approach to implement integrated capacitors with an excellent capacitance density, called the “3-D embedded capacitor,” is investigated. It is realized by embedding metal-insulator-metal (MIM) layers onto the trenches of through-silicon vias prior to copper filling. An ultrahigh capacitance density of 5621.8 nF/mm 2 was envisioned according to our model, which is ~13× of 440.0 nF/mm 2 from a conventional trench capacitor with the same design parameters. A set of prototypes was fabricated and characterized for assessment of structural integrity and electrical performance of the 3-D embedded capacitors. Scanning electron microscope, transmission electron microscope, and energy-dispersive X-ray spectroscopy analysis results show a good step coverage and stoichiometry of the MIM layers deposited. The capacitance density of up to 3856.4 nF/mm 2 was achieved for the prototypes with MIM layers formed by atomic layer deposition. A leakage current density as low as 1.61×10 -7 A/cm 2 at 4.3 V and a breakdown voltage greater than 9.5 V were measured for a sample with a capacitance density of 3776.6 nF/mm 2 .