Three-dimensional capacitor embedded in fully Cu-filled through-silicon via and its thermo-mechanical reliability for power delivery applications

• Main Authors: Lin, Ye, Apriyana, Anak Agung Alit, Hong, Yu Li, Tan, Chuan Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering::Semiconductors; Through-silicon Vias; MIM Capacitors
• Online Access: https://hdl.handle.net/10356/144083
• Institution: Nanyang Technological University

This paper demonstrates the successful integration of three-dimensional (3-D) metal-insulator-metal (MIM) capacitors embedded in fully-filled Cu TSVs with diameter of 10 and 20 μm. Their thermo-mechanical reliability has been studied with both physical characterizations and electrical characterizations. The structures of D10 and D20 test vehicles remain intact after through-silicon via (TSV) Cu filling. However, it is found in TEM images that both peaks of Si scallops and the Al2O3 dielectric layer in MIM capacitor were impaired for D30 test vehicle. The leakage current density of MIM capacitors is 4.0×10 -9 , 4.1×10 -8 , 1.1×10 -6 , and 7.4×10 -1 A/cm 2 for D00, D10, D20, and D30 test vehicles, respectively. The results support the evidence from transmission electron microscopy (TEM), showing that the Al2O3 dielectric layer in the MIM capacitor is indeed impaired and loses its insulating property. Ultrahigh capacitance density is obtained as 6,547.1 nF/mm 2 and 7,091.7 nF/mm 2 for D10 and D20 test vehicles, respectively. Furthermore, some simulation work has been carried out to showcase its application as decoupling capacitor in a power delivery network (PDN). The inserted 3-D MIM capacitor helps to keep the target impedance below 2.5 Ω over a wide range of 0-5 GHz for an applied specific integrated circuit-high bandwidth memory (ASIC-HBM) system. And the voltage fluctuation is also reduced from ~3.0 to ~1.0 V by as much as ~66.7%.