TSV-integrated surface electrode ion trap for scalable quantum information processing

• Main Authors: Zhao, Peng, Likforman, J. P., Li, Hong Yu, Tao, Jing, Henner, T., Lim, Yu Dian, Seit, W. W., Tan, Chuan Seng, Guidoni, Luca
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering::Semiconductors; Science::Physics; Qubit; TSV
• Online Access: https://hdl.handle.net/10356/148248
• Institution: Nanyang Technological University

In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrodes numbers and evolving complexity. The integration of TSVs reduces the form factor of ion trap by more than 80%, minimizing parasitic capacitance from 32 to 3 pF. A low RF dissipation is achieved in spite of the absence of ground screening layer. The entire fabrication process is on 12-inch wafer and compatible with established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (~30 minutes) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.