Area-saving technique for low-error redundant binary fixed-width multiplier implementation
A recently proposed architecture of redundant binary fixed-width multiplier was shown to outperform several normal binary fixed-width multipliers in terms of accuracy. However, its merit due to the carry-free addition property of the binary...
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Main Authors: | Juang, Tso Bing, Wei, Chi Chung, Chang, Chip Hong |
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Other Authors: | School of Electrical and Electronic Engineering |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2010
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/80023 http://hdl.handle.net/10220/6356 http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403938 |
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Institution: | Nanyang Technological University |
Language: | English |
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