Scalable model of on-wafer interconnects for high-speed CMOS ICs

• Main Authors: Shi, Xiaomeng, Yeo, Kiat Seng, Ma, Jianguo, Do, Manh Anh, Li, Erping
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/91415; http://hdl.handle.net/10220/4713
• Institution: Nanyang Technological University

This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two- blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the...