Scalable model of on-wafer interconnects for high-speed CMOS ICs

Scalable model of on-wafer interconnects for high-speed CMOS ICs

This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two- blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the...

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書目詳細資料
Main Authors:	Shi, Xiaomeng, Yeo, Kiat Seng, Ma, Jianguo, Do, Manh Anh, Li, Erping
其他作者:	School of Electrical and Electronic Engineering
格式:	Article
語言:	English
出版:	2009
主題:	DRNTU::Engineering::Electrical and electronic engineering
在線閱讀:	https://hdl.handle.net/10356/91415 http://hdl.handle.net/10220/4713
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	Nanyang Technological University
語言:	English

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