Positive bias-induced Vth instability in graphene field effect transistors

• Main Authors: Liu, W. J., Fang, Z., Wang, Z. R., Wang, F., Wu, L., Zhang, J. F., Wei, J., Zhu, H. L., Sun, Xiaowei, Tran, Xuan Anh, Ng, Geok Ing, Yu, Hongyu
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/98513; http://hdl.handle.net/10220/11342
• Institution: Nanyang Technological University

In this letter, we report positive bias-induced Vth instability in single and multilayer graphene field effect transistors (GFETs) with back-gate SiO2 dielectric. The ΔVth of GFETs increases as stressing time and voltage increases, and tends to saturate after long stressing time. In the meanwhile, it does not show much dependence on gate length, width, and the number of graphene layers. The 1/f noise measurement indicates no newly generated traps in SiO2/graphene interface caused by positive bias stressing. Mobility is seen to degrade with temperature in- creasing. The degradation is believed to be caused by the trapped electrons in bulk SiO2 or SiO2/graphene interface and trap generation in bulk SiO2.