Positive bias-induced Vth instability in graphene field effect transistors
In this letter, we report positive bias-induced Vth instability in single and multilayer graphene field effect transistors (GFETs) with back-gate SiO2 dielectric. The ΔVth of GFETs increases as stressing time and voltage increases, and tends to saturate after long stressing time. In the meanwhile, i...
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sg-ntu-dr.10356-985132020-03-07T14:00:30Z Positive bias-induced Vth instability in graphene field effect transistors Liu, W. J. Fang, Z. Wang, Z. R. Wang, F. Wu, L. Zhang, J. F. Wei, J. Zhu, H. L. Sun, Xiaowei Tran, Xuan Anh Ng, Geok Ing Yu, Hongyu School of Electrical and Electronic Engineering A*STAR SIMTech DRNTU::Engineering::Electrical and electronic engineering In this letter, we report positive bias-induced Vth instability in single and multilayer graphene field effect transistors (GFETs) with back-gate SiO2 dielectric. The ΔVth of GFETs increases as stressing time and voltage increases, and tends to saturate after long stressing time. In the meanwhile, it does not show much dependence on gate length, width, and the number of graphene layers. The 1/f noise measurement indicates no newly generated traps in SiO2/graphene interface caused by positive bias stressing. Mobility is seen to degrade with temperature in- creasing. The degradation is believed to be caused by the trapped electrons in bulk SiO2 or SiO2/graphene interface and trap generation in bulk SiO2. 2013-07-12T08:46:16Z 2019-12-06T19:56:23Z 2013-07-12T08:46:16Z 2019-12-06T19:56:23Z 2012 2012 Journal Article https://hdl.handle.net/10356/98513 http://hdl.handle.net/10220/11342 10.1109/LED.2011.2181150 en IEEE electron device letters © 2012 IEEE. |
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DRNTU::Engineering::Electrical and electronic engineering Liu, W. J. Fang, Z. Wang, Z. R. Wang, F. Wu, L. Zhang, J. F. Wei, J. Zhu, H. L. Sun, Xiaowei Tran, Xuan Anh Ng, Geok Ing Yu, Hongyu Positive bias-induced Vth instability in graphene field effect transistors |
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In this letter, we report positive bias-induced Vth instability in single and multilayer graphene field effect transistors (GFETs) with back-gate SiO2 dielectric. The ΔVth of GFETs increases as stressing time and voltage increases, and tends to saturate after long stressing time. In the meanwhile, it does not show much dependence on gate length, width, and the number of graphene layers. The 1/f noise measurement indicates no newly generated traps in SiO2/graphene interface caused by positive bias stressing. Mobility is seen to degrade with temperature in- creasing. The degradation is believed to be caused by the trapped electrons in bulk SiO2 or SiO2/graphene interface and trap generation in bulk SiO2. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Liu, W. J. Fang, Z. Wang, Z. R. Wang, F. Wu, L. Zhang, J. F. Wei, J. Zhu, H. L. Sun, Xiaowei Tran, Xuan Anh Ng, Geok Ing Yu, Hongyu |
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Article |
author |
Liu, W. J. Fang, Z. Wang, Z. R. Wang, F. Wu, L. Zhang, J. F. Wei, J. Zhu, H. L. Sun, Xiaowei Tran, Xuan Anh Ng, Geok Ing Yu, Hongyu |
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Liu, W. J. |
title |
Positive bias-induced Vth instability in graphene field effect transistors |
title_short |
Positive bias-induced Vth instability in graphene field effect transistors |
title_full |
Positive bias-induced Vth instability in graphene field effect transistors |
title_fullStr |
Positive bias-induced Vth instability in graphene field effect transistors |
title_full_unstemmed |
Positive bias-induced Vth instability in graphene field effect transistors |
title_sort |
positive bias-induced vth instability in graphene field effect transistors |
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2013 |
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https://hdl.handle.net/10356/98513 http://hdl.handle.net/10220/11342 |
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1681047468212486144 |