Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning

Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning

10.1016/j.tsf.2005.09.152

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Bibliographic Details
Main Authors: Bliznetsov, V., Kumar, R., Lin, H., Ang, K.-W., Yoo, W.J., Du, A.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Subjects:
Dipole ring magnetron
Hard mask
Photoresist trimming
Sub-50 nm
Online Access:http://scholarbank.nus.edu.sg/handle/10635/70623
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Institution: National University of Singapore
Description
Summary:10.1016/j.tsf.2005.09.152

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