Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning

• Main Authors: Bliznetsov, V., Kumar, R., Lin, H., Ang, K.-W., Yoo, W.J., Du, A.
• Other Authors: ELECTRICAL & COMPUTER ENGINEERING
• Format: Conference or Workshop Item
• Published: 2014
• Subjects: Dipole ring magnetron; Hard mask; Photoresist trimming; Sub-50 nm
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/70623
• Institution: National University of Singapore

10.1016/j.tsf.2005.09.152