Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning

Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning

10.1016/j.tsf.2005.09.152

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Bibliographic Details
Main Authors: Bliznetsov, V., Kumar, R., Lin, H., Ang, K.-W., Yoo, W.J., Du, A.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Subjects:
Dipole ring magnetron
Hard mask
Photoresist trimming
Sub-50 nm
Online Access:http://scholarbank.nus.edu.sg/handle/10635/70623
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Institution: National University of Singapore
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spelling sg-nus-scholar.10635-706232023-10-30T07:40:12Z Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning Bliznetsov, V. Kumar, R. Lin, H. Ang, K.-W. Yoo, W.J. Du, A. ELECTRICAL & COMPUTER ENGINEERING Dipole ring magnetron Hard mask Photoresist trimming Sub-50 nm 10.1016/j.tsf.2005.09.152 Thin Solid Films 504 1-2 117-120 THSFA 2014-06-19T03:14:17Z 2014-06-19T03:14:17Z 2006-05-10 Conference Paper Bliznetsov, V., Kumar, R., Lin, H., Ang, K.-W., Yoo, W.J., Du, A. (2006-05-10). Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning. Thin Solid Films 504 (1-2) : 117-120. ScholarBank@NUS Repository. https://doi.org/10.1016/j.tsf.2005.09.152 00406090 http://scholarbank.nus.edu.sg/handle/10635/70623 000236486200028 Scopus
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
topic Dipole ring magnetron
Hard mask
Photoresist trimming
Sub-50 nm
spellingShingle Dipole ring magnetron
Hard mask
Photoresist trimming
Sub-50 nm
Bliznetsov, V.
Kumar, R.
Lin, H.
Ang, K.-W.
Yoo, W.J.
Du, A.
Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
description 10.1016/j.tsf.2005.09.152
author2 ELECTRICAL & COMPUTER ENGINEERING
author_facet ELECTRICAL & COMPUTER ENGINEERING
Bliznetsov, V.
Kumar, R.
Lin, H.
Ang, K.-W.
Yoo, W.J.
Du, A.
format Conference or Workshop Item
author Bliznetsov, V.
Kumar, R.
Lin, H.
Ang, K.-W.
Yoo, W.J.
Du, A.
author_sort Bliznetsov, V.
title Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
title_short Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
title_full Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
title_fullStr Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
title_full_unstemmed Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
title_sort integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
publishDate 2014
url http://scholarbank.nus.edu.sg/handle/10635/70623
_version_ 1781783172116119552

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