Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning

10.1016/j.tsf.2005.09.152

Saved in:
Bibliographic Details
Main Authors: Bliznetsov, V., Kumar, R., Lin, H., Ang, K.-W., Yoo, W.J., Du, A.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Subjects:
Online Access:http://scholarbank.nus.edu.sg/handle/10635/70623
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: National University of Singapore