Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly

• Main Authors: Zhao, Peng, Li, Hong Yu, Lim, Yu Dian, Hu, Liangxing, Seit, Wen Wei, Guidoni, Luca, Tan, Chuan Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2023
• Subjects: Engineering::Electrical and electronic engineering::Electronic packaging; Advanced Integration; Ceramic Pin Ggrid Array
• Online Access: https://hdl.handle.net/10356/166180
• Institution: Nanyang Technological University

To alleviate the heat dissipation issue of through silicon via (TSV) integrated ion trap on glass interposer, a ceramic pin grid array (CPGA) with built-in redistribution layer (RDL) is demonstrated to locate the trap directly. This patterned RDL has internal connection to the backside CPGA pin, facilitating locally flexible signal rerouting. The glass interposer with poor thermal conductivity can be eliminated. The design consideration and fabrication steps of customized CPGA are presented. The leakage current and parasitic capacitance are characterized using I-V and C-V tests respectively. It is found that the customized CPGA has a superior insulation performance: the averaged resistance between two arbitrary RDL pads is 3.2 × 1012Ohm, which is three orders of magnitude higher than that of TSV integrated ion trap itself. The capacitance between RF and central DC RDL pads is ∼1 pF, indicating low RF loss. Based on finite element modelling result, the temperature increase of trap surface on customized CPGA is able to maintain ~3 K at a given power of 0.1 W, significantly lower than that of trap on glass interposer (∼35 K). A compact assembly architecture with good thermal dissipation capacity is demonstrated for ion trap devices.