Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly
To alleviate the heat dissipation issue of through silicon via (TSV) integrated ion trap on glass interposer, a ceramic pin grid array (CPGA) with built-in redistribution layer (RDL) is demonstrated to locate the trap directly. This patterned RDL has internal connection to the backside CPGA pin, fac...
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sg-ntu-dr.10356-1661802023-04-20T05:46:18Z Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly Zhao, Peng Li, Hong Yu Lim, Yu Dian Hu, Liangxing Seit, Wen Wei Guidoni, Luca Tan, Chuan Seng School of Electrical and Electronic Engineering 2022 IEEE 9th Electronics System-Integration Technology Conference (ESTC) Engineering::Electrical and electronic engineering::Electronic packaging Advanced Integration Ceramic Pin Ggrid Array To alleviate the heat dissipation issue of through silicon via (TSV) integrated ion trap on glass interposer, a ceramic pin grid array (CPGA) with built-in redistribution layer (RDL) is demonstrated to locate the trap directly. This patterned RDL has internal connection to the backside CPGA pin, facilitating locally flexible signal rerouting. The glass interposer with poor thermal conductivity can be eliminated. The design consideration and fabrication steps of customized CPGA are presented. The leakage current and parasitic capacitance are characterized using I-V and C-V tests respectively. It is found that the customized CPGA has a superior insulation performance: the averaged resistance between two arbitrary RDL pads is 3.2 × 1012Ohm, which is three orders of magnitude higher than that of TSV integrated ion trap itself. The capacitance between RF and central DC RDL pads is ∼1 pF, indicating low RF loss. Based on finite element modelling result, the temperature increase of trap surface on customized CPGA is able to maintain ~3 K at a given power of 0.1 W, significantly lower than that of trap on glass interposer (∼35 K). A compact assembly architecture with good thermal dissipation capacity is demonstrated for ion trap devices. National Research Foundation (NRF) This work is supported by the National Research Foundation, Singapore, under its ANR-NRF Joint Grant Call (NRF2020-NRF-ANR073 HIT). 2023-04-20T05:46:18Z 2023-04-20T05:46:18Z 2022 Conference Paper Zhao, P., Li, H. Y., Lim, Y. D., Hu, L., Seit, W. W., Guidoni, L. & Tan, C. S. (2022). Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly. 2022 IEEE 9th Electronics System-Integration Technology Conference (ESTC). https://dx.doi.org/10.1109/ESTC55720.2022.9939436 9781665489478 https://hdl.handle.net/10356/166180 10.1109/ESTC55720.2022.9939436 2-s2.0-85143131870 en NRF2020-NRF-ANR073 HIT © 2022 IEEE. All rights reserved. |
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Engineering::Electrical and electronic engineering::Electronic packaging Advanced Integration Ceramic Pin Ggrid Array Zhao, Peng Li, Hong Yu Lim, Yu Dian Hu, Liangxing Seit, Wen Wei Guidoni, Luca Tan, Chuan Seng Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly |
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To alleviate the heat dissipation issue of through silicon via (TSV) integrated ion trap on glass interposer, a ceramic pin grid array (CPGA) with built-in redistribution layer (RDL) is demonstrated to locate the trap directly. This patterned RDL has internal connection to the backside CPGA pin, facilitating locally flexible signal rerouting. The glass interposer with poor thermal conductivity can be eliminated. The design consideration and fabrication steps of customized CPGA are presented. The leakage current and parasitic capacitance are characterized using I-V and C-V tests respectively. It is found that the customized CPGA has a superior insulation performance: the averaged resistance between two arbitrary RDL pads is 3.2 × 1012Ohm, which is three orders of magnitude higher than that of TSV integrated ion trap itself. The capacitance between RF and central DC RDL pads is ∼1 pF, indicating low RF loss. Based on finite element modelling result, the temperature increase of trap surface on customized CPGA is able to maintain ~3 K at a given power of 0.1 W, significantly lower than that of trap on glass interposer (∼35 K). A compact assembly architecture with good thermal dissipation capacity is demonstrated for ion trap devices. |
author2 |
School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Zhao, Peng Li, Hong Yu Lim, Yu Dian Hu, Liangxing Seit, Wen Wei Guidoni, Luca Tan, Chuan Seng |
format |
Conference or Workshop Item |
author |
Zhao, Peng Li, Hong Yu Lim, Yu Dian Hu, Liangxing Seit, Wen Wei Guidoni, Luca Tan, Chuan Seng |
author_sort |
Zhao, Peng |
title |
Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly |
title_short |
Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly |
title_full |
Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly |
title_fullStr |
Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly |
title_full_unstemmed |
Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly |
title_sort |
ceramic pin grid array with built-in interconnects to locate tsv integrated ion trap for wire bonding-free assembly |
publishDate |
2023 |
url |
https://hdl.handle.net/10356/166180 |
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1764208058029834240 |