Ceramic pin grid array with built-in interconnects to locate TSV integrated ion trap for wire bonding-free assembly

• Main Authors: Zhao, Peng, Li, Hong Yu, Lim, Yu Dian, Hu, Liangxing, Seit, Wen Wei, Guidoni, Luca, Tan, Chuan Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2023
• Subjects: Engineering::Electrical and electronic engineering::Electronic packaging; Advanced Integration; Ceramic Pin Ggrid Array
• Online Access: https://hdl.handle.net/10356/166180
• Institution: Nanyang Technological University

To alleviate the heat dissipation issue of through silicon via (TSV) integrated ion trap on glass interposer, a ceramic pin grid array (CPGA) with built-in redistribution layer (RDL) is demonstrated to locate the trap directly. This patterned RDL has internal connection to the backside CPGA pin, fac...