ASIC implementation of a high speed and low power scalar product computation unit
This project involves the design, synthesis and placement & routing of improved 16-bit 15-element unsigned inner product architecture. Improvement to the design were made in the carry free addition stage, which is also known as column compression stage or reduction stage, whereby counters are in...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | |
| التنسيق: | Final Year Project |
| اللغة: | English |
| منشور في: |
2009
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| الموضوعات: | |
| الوصول للمادة أونلاين: | http://hdl.handle.net/10356/16733 |
| الوسوم: |
إضافة وسم
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| المؤسسة: | Nanyang Technological University |
| اللغة: | English |