ASIC implementation of a high speed and low power scalar product computation unit

ASIC implementation of a high speed and low power scalar product computation unit

This project involves the design, synthesis and placement & routing of improved 16-bit 15-element unsigned inner product architecture. Improvement to the design were made in the carry free addition stage, which is also known as column compression stage or reduction stage, whereby counters are in...

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書目詳細資料
主要作者:	Low, Jeremy Yung Shern.
其他作者:	Chan Pak Kwong
格式:	Final Year Project
語言:	English
出版:	2009
主題:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
在線閱讀:	http://hdl.handle.net/10356/16733
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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