Simplified Assembly of Through-Silicon-Via Integrated Ion Traps

The scalability of surface electrode ion traps has been progressively improved with the on-chip integration of conventionally bulk components. Based on the development of through silicon via (TSV) integrated ion trap, in this work, we further simplify the back-end assembly process by patterning...

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Main Authors: Zhao, Peng, Li, Hong Yu, Likforman, Jean-Pierre, Henner, Theo, Lim, Yu Dian, Hu, Liang Xing, Seit, Wen Wei, Luca, Guidoni, Tan, Chuan Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2023
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Online Access:https://hdl.handle.net/10356/170177
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-1701772023-09-01T15:38:57Z Simplified Assembly of Through-Silicon-Via Integrated Ion Traps Zhao, Peng Li, Hong Yu Likforman, Jean-Pierre Henner, Theo Lim, Yu Dian Hu, Liang Xing Seit, Wen Wei Luca, Guidoni Tan, Chuan Seng School of Electrical and Electronic Engineering Institute of Microelectronics, A*STAR Engineering::Electrical and electronic engineering::Microelectronics Ceramic Pin Grid Array Redistribution Layer Surface Electrode Ion Trap Through-Silicon Vias The scalability of surface electrode ion traps has been progressively improved with the on-chip integration of conventionally bulk components. Based on the development of through silicon via (TSV) integrated ion trap, in this work, we further simplify the back-end assembly process by patterning a redistribution layer (RDL) onto customized ceramic pin grid array (CPGA) package. This RDL has internal connection with CPGA pin on the back side, rerouting the electrical signal and facilitating the direct bonding of TSV trap and CPGA. The patterned neighboring RDL has an averaged resistance of 4.5 × 1012 , three orders of magnitude higher than that of TSV trap itself. As compared to the previous assembly (glass interposer wire bonded to a conventional CPGA), a small parasitic capacitance increase of 0.1 pF of the customized CPGA is observed. Radio frequency (RF) electrical tests indicate that the trap on customized CPGA will not induce additional power loss. Meanwhile, due to the high thermal conductivity of ceramic materials, the heat dissipation capability of customized CPGA is boosted. The functionality of TSV trap on customized CPGA is also demonstrated by trapping and laser cooling the 88Sr+ ions. The measured heating rate (21 quanta per millisecond for an axial frequency of 300 kHz) is comparable with the trap assembled in previous approach. This indicates that the CPGA with built-in RDL is fully compatible with ion trapping applications, providing a new approach towards compact, flexible, and robust ion trap assembly. National Research Foundation (NRF) Submitted/Accepted version This work is supported by National Research Foundation, Singapore, under its ANR-NRF Joint Grant Call (NRF2020-NRF-ANR073 HIT). 2023-08-31T01:04:21Z 2023-08-31T01:04:21Z 2023 Journal Article Zhao, P., Li, H. Y., Likforman, J., Henner, T., Lim, Y. D., Hu, L. X., Seit, W. W., Luca, G. & Tan, C. S. (2023). Simplified Assembly of Through-Silicon-Via Integrated Ion Traps. IEEE Transactions On Components, Packaging and Manufacturing Technology. https://dx.doi.org/10.1109/TCPMT.2023.3309831 2156-3950 https://hdl.handle.net/10356/170177 10.1109/TCPMT.2023.3309831 en NRF2020-NRF-ANR073 HIT IEEE Transactions on Components, Packaging and Manufacturing Technology © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCPMT.2023.3309831. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering::Microelectronics
Ceramic Pin Grid Array
Redistribution Layer
Surface Electrode Ion Trap
Through-Silicon Vias
spellingShingle Engineering::Electrical and electronic engineering::Microelectronics
Ceramic Pin Grid Array
Redistribution Layer
Surface Electrode Ion Trap
Through-Silicon Vias
Zhao, Peng
Li, Hong Yu
Likforman, Jean-Pierre
Henner, Theo
Lim, Yu Dian
Hu, Liang Xing
Seit, Wen Wei
Luca, Guidoni
Tan, Chuan Seng
Simplified Assembly of Through-Silicon-Via Integrated Ion Traps
description The scalability of surface electrode ion traps has been progressively improved with the on-chip integration of conventionally bulk components. Based on the development of through silicon via (TSV) integrated ion trap, in this work, we further simplify the back-end assembly process by patterning a redistribution layer (RDL) onto customized ceramic pin grid array (CPGA) package. This RDL has internal connection with CPGA pin on the back side, rerouting the electrical signal and facilitating the direct bonding of TSV trap and CPGA. The patterned neighboring RDL has an averaged resistance of 4.5 × 1012 , three orders of magnitude higher than that of TSV trap itself. As compared to the previous assembly (glass interposer wire bonded to a conventional CPGA), a small parasitic capacitance increase of 0.1 pF of the customized CPGA is observed. Radio frequency (RF) electrical tests indicate that the trap on customized CPGA will not induce additional power loss. Meanwhile, due to the high thermal conductivity of ceramic materials, the heat dissipation capability of customized CPGA is boosted. The functionality of TSV trap on customized CPGA is also demonstrated by trapping and laser cooling the 88Sr+ ions. The measured heating rate (21 quanta per millisecond for an axial frequency of 300 kHz) is comparable with the trap assembled in previous approach. This indicates that the CPGA with built-in RDL is fully compatible with ion trapping applications, providing a new approach towards compact, flexible, and robust ion trap assembly.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Zhao, Peng
Li, Hong Yu
Likforman, Jean-Pierre
Henner, Theo
Lim, Yu Dian
Hu, Liang Xing
Seit, Wen Wei
Luca, Guidoni
Tan, Chuan Seng
format Article
author Zhao, Peng
Li, Hong Yu
Likforman, Jean-Pierre
Henner, Theo
Lim, Yu Dian
Hu, Liang Xing
Seit, Wen Wei
Luca, Guidoni
Tan, Chuan Seng
author_sort Zhao, Peng
title Simplified Assembly of Through-Silicon-Via Integrated Ion Traps
title_short Simplified Assembly of Through-Silicon-Via Integrated Ion Traps
title_full Simplified Assembly of Through-Silicon-Via Integrated Ion Traps
title_fullStr Simplified Assembly of Through-Silicon-Via Integrated Ion Traps
title_full_unstemmed Simplified Assembly of Through-Silicon-Via Integrated Ion Traps
title_sort simplified assembly of through-silicon-via integrated ion traps
publishDate 2023
url https://hdl.handle.net/10356/170177
_version_ 1779156354623078400