Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices

Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices

US6010954

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Bibliographic Details
Main Authors: HO, CHAW SING, KARUNASIRI, R. P. G., CHUA, SOO JIN, PEY, KIN LEONG, LEE, KONG HEAN
Other Authors: ELECTRICAL ENGINEERING
Format: Patent
Published: 2012
Online Access:http://scholarbank.nus.edu.sg/handle/10635/32568
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Institution: National University of Singapore
id sg-nus-scholar.10635-32568
record_format dspace
spelling sg-nus-scholar.10635-325682015-07-29T07:03:40Z Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices HO, CHAW SING KARUNASIRI, R. P. G. CHUA, SOO JIN PEY, KIN LEONG LEE, KONG HEAN ELECTRICAL ENGINEERING CHARTERED SEMICONDUCTOR MANUFACTURING, LTD. (SINGAPORE, SG) NATIONAL UNIVERSITY OF SINGAPORE US6010954 Granted Patent 2012-05-02T02:27:09Z 2012-05-02T02:27:09Z 2000-01-04 Patent HO, CHAW SING,KARUNASIRI, R. P. G.,CHUA, SOO JIN,PEY, KIN LEONG,LEE, KONG HEAN (2000-01-04). Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/32568 NOT_IN_WOS PatSnap
institution National University of Singapore
building NUS Library
country Singapore
collection ScholarBank@NUS
description US6010954
author2 ELECTRICAL ENGINEERING
author_facet ELECTRICAL ENGINEERING
HO, CHAW SING
KARUNASIRI, R. P. G.
CHUA, SOO JIN
PEY, KIN LEONG
LEE, KONG HEAN
format Patent
author HO, CHAW SING
KARUNASIRI, R. P. G.
CHUA, SOO JIN
PEY, KIN LEONG
LEE, KONG HEAN
spellingShingle HO, CHAW SING
KARUNASIRI, R. P. G.
CHUA, SOO JIN
PEY, KIN LEONG
LEE, KONG HEAN
Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices
author_sort HO, CHAW SING
title Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices
title_short Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices
title_full Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices
title_fullStr Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices
title_full_unstemmed Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices
title_sort cmos gate architecture for integration of salicide process in sub 0.1. .mum devices
publishDate 2012
url http://scholarbank.nus.edu.sg/handle/10635/32568
_version_ 1681081247207522304

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