Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices
US6010954
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Main Authors: | HO, CHAW SING, KARUNASIRI, R. P. G., CHUA, SOO JIN, PEY, KIN LEONG, LEE, KONG HEAN |
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Other Authors: | ELECTRICAL ENGINEERING |
Format: | Patent |
Published: |
2012
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Online Access: | http://scholarbank.nus.edu.sg/handle/10635/32568 |
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Institution: | National University of Singapore |
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