Cmos gate architecture for integration of salicide process in sub 0.1. .muM devices

• Main Authors: HO, CHAW SING, KARUNASIRI, R. P. G., CHUA, SOO JIN, PEY, KIN LEONG, LEE, KONG HEAN
• 其他作者: ELECTRICAL ENGINEERING
• 格式: Patent
• 出版: 2012
• 在線閱讀: http://scholarbank.nus.edu.sg/handle/10635/32568

US6010954