A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate

10.1109/LED.2004.832535

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Main Authors:	Ren, C., Yu, H.Y., Kang, J.F., Wang, X.P., Ma, H.H.H., Yeo, Y.-C., Chan, D.S.H., Li, M.-F., Kwong, D.-L.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Article
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/81863
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Institution:	National University of Singapore

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spelling	sg-nus-scholar.10635-818632023-10-29T22:27:29Z A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate Ren, C. Yu, H.Y. Kang, J.F. Wang, X.P. Ma, H.H.H. Yeo, Y.-C. Chan, D.S.H. Li, M.-F. Kwong, D.-L. ELECTRICAL & COMPUTER ENGINEERING 10.1109/LED.2004.832535 IEEE Electron Device Letters 25 8 580-582 EDLED 2014-10-07T04:22:35Z 2014-10-07T04:22:35Z 2004-08 Article Ren, C., Yu, H.Y., Kang, J.F., Wang, X.P., Ma, H.H.H., Yeo, Y.-C., Chan, D.S.H., Li, M.-F., Kwong, D.-L. (2004-08). A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate. IEEE Electron Device Letters 25 (8) : 580-582. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2004.832535 07413106 http://scholarbank.nus.edu.sg/handle/10635/81863 000222905100022 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
description	10.1109/LED.2004.832535
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Ren, C. Yu, H.Y. Kang, J.F. Wang, X.P. Ma, H.H.H. Yeo, Y.-C. Chan, D.S.H. Li, M.-F. Kwong, D.-L.
format	Article
author	Ren, C. Yu, H.Y. Kang, J.F. Wang, X.P. Ma, H.H.H. Yeo, Y.-C. Chan, D.S.H. Li, M.-F. Kwong, D.-L.
spellingShingle	Ren, C. Yu, H.Y. Kang, J.F. Wang, X.P. Ma, H.H.H. Yeo, Y.-C. Chan, D.S.H. Li, M.-F. Kwong, D.-L. A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate
author_sort	Ren, C.
title	A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate
title_short	A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate
title_full	A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate
title_fullStr	A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate
title_full_unstemmed	A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate
title_sort	dual-metal gate integration process for cmos with sub-1-nm eot hfo2 by using hfn replacement gate
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/81863
_version_	1781784001744207872

A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate

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