Performance characterisation and design issues of low voltage BiCMOS digital circuits
This report addresses the work done on the power and speed optimisation of 4 different BiCMOS gate structures using 3 sub-micron technologies; namely 1.5V/0.35um, 2.2V/0.5|im and 3.3V/0.8(im for several fan-in fan-out conditions. The BiCMOS structures studied in this project encompass the Bootstrapp...
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Main Author: | Cheong, Chee Seng. |
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Other Authors: | School of Electrical and Electronic Engineering |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2008
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Subjects: | |
Online Access: | http://hdl.handle.net/10356/13150 |
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Institution: | Nanyang Technological University |
Language: | English |
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