Design of ultra-low power asynchronous-logic quasi-delay-insensitive circuit templates

• Main Author: Chng, Clive Kuan Nee.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/45915
• Institution: Nanyang Technological University

This report presents the design of Ultra-low power asynchronous Quasi-Delay-Insensitive (QDI) library cells and circuits templates using the CMOS 65nm Bulk process technology. Asynchronous systems are self-timed circuits that employ hand-shaking protocols instead of relying on a global clock to comm...