An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads
Parallel graph-oriented applications expressed in the Bulk-Synchronous Parallel (BSP) and Token Dataflow compute models generate highly-structured communication workloads from messages propagating along graph edges. We can statially expose this structure to traffic compilers and optimization tools t...
Saved in:
Main Authors: | Kapre, Nachiket, Dehon, André |
---|---|
Other Authors: | School of Computer Engineering |
Format: | Article |
Language: | English |
Published: |
2015
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/81118 http://hdl.handle.net/10220/39124 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Spatial hardware implementation for sparse graph algorithms in GraphStep
by: Delorimier, Michael, et al.
Published: (2015) -
Custom FPGA-based soft-processors for sparse graph acceleration
by: Kapre, Nachiket
Published: (2015) -
VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration
by: Kapre, Nachiket, et al.
Published: (2015) -
Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs
by: Kapre, Nachiket, et al.
Published: (2015) -
Breaking Sequential Dependencies in FPGA-Based Sparse LU Factorization
by: Siddhartha, et al.
Published: (2015)