Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps

• Main Authors: Sa, N., Kang, J.F., Yang, H., Liu, X.Y., He, Y.D., Han, R.Q., Ren, C., Yu, H.Y., Chan, D.S.H., Kwong, D.-L.
• Other Authors: ELECTRICAL & COMPUTER ENGINEERING
• Format: Article
• Published: 2014
• Subjects: Electric stress-induced defect generation (ESIDG); High-κ gate dielectric; Positive-bias temperature instability (PBTI); Reaction-diffusion (R-D) model
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/82674
• Institution: National University of Singapore

10.1109/LED.2005.853683