Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps

10.1109/LED.2005.853683

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Bibliographic Details
Main Authors:	Sa, N., Kang, J.F., Yang, H., Liu, X.Y., He, Y.D., Han, R.Q., Ren, C., Yu, H.Y., Chan, D.S.H., Kwong, D.-L.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Article
Published:	2014
Subjects:	Electric stress-induced defect generation (ESIDG) High-κ gate dielectric Positive-bias temperature instability (PBTI) Reaction-diffusion (R-D) model
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/82674
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Institution:	National University of Singapore

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spelling	sg-nus-scholar.10635-826742024-11-11T07:32:15Z Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps Sa, N. Kang, J.F. Yang, H. Liu, X.Y. He, Y.D. Han, R.Q. Ren, C. Yu, H.Y. Chan, D.S.H. Kwong, D.-L. ELECTRICAL & COMPUTER ENGINEERING Electric stress-induced defect generation (ESIDG) High-κ gate dielectric Positive-bias temperature instability (PBTI) Reaction-diffusion (R-D) model 10.1109/LED.2005.853683 IEEE Electron Device Letters 26 9 610-612 EDLED 2014-10-07T04:32:10Z 2014-10-07T04:32:10Z 2005-09 Article Sa, N., Kang, J.F., Yang, H., Liu, X.Y., He, Y.D., Han, R.Q., Ren, C., Yu, H.Y., Chan, D.S.H., Kwong, D.-L. (2005-09). Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps. IEEE Electron Device Letters 26 (9) : 610-612. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2005.853683 07413106 http://scholarbank.nus.edu.sg/handle/10635/82674 000231577900004 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Electric stress-induced defect generation (ESIDG) High-κ gate dielectric Positive-bias temperature instability (PBTI) Reaction-diffusion (R-D) model
spellingShingle	Electric stress-induced defect generation (ESIDG) High-κ gate dielectric Positive-bias temperature instability (PBTI) Reaction-diffusion (R-D) model Sa, N. Kang, J.F. Yang, H. Liu, X.Y. He, Y.D. Han, R.Q. Ren, C. Yu, H.Y. Chan, D.S.H. Kwong, D.-L. Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps
description	10.1109/LED.2005.853683
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Sa, N. Kang, J.F. Yang, H. Liu, X.Y. He, Y.D. Han, R.Q. Ren, C. Yu, H.Y. Chan, D.S.H. Kwong, D.-L.
format	Article
author	Sa, N. Kang, J.F. Yang, H. Liu, X.Y. He, Y.D. Han, R.Q. Ren, C. Yu, H.Y. Chan, D.S.H. Kwong, D.-L.
author_sort	Sa, N.
title	Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps
title_short	Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps
title_full	Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps
title_fullStr	Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps
title_full_unstemmed	Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps
title_sort	mechanism of positive-bias temperature instability in sub-1-nm tan/hfn/hfo2 gate stack with low preexisting traps
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/82674
_version_	1821205151214469120

Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps

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