IDDQ testing for deep sub-micron SOC

• Main Author: Ye, Xiaocheng.
• Other Authors: Lau, Wai Shing
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
• Online Access: http://hdl.handle.net/10356/3891
• Institution: Nanyang Technological University

The focus of this project is to study the application of new IDDQ testing schemes to deep-submicron SoC (System on Chip), for example, a 32-bit DSP microcontroller. Power partitioning has been applied to reduce the circuit scale under test from design point of view.