0.13-micron CMOS device characterization
This project emphasizes more on the transistor electrical characterization aspect as the input Front End of Line parameters are varied. This report covers the characterization of a fully working 0.13 um device with three layer metal copper Dual Damascene backend process.
Saved in:
Main Author: | Lazuardi, Stephen |
---|---|
Other Authors: | Krishnamachar Prasad |
Format: | Theses and Dissertations |
Published: |
2008
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/4564 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Similar Items
-
Application of phase shift masking to sub-0.13 micron lithography
by: Koo, Chee Kiong.
Published: (2008) -
Calibration methodology for predictive simulation of sub-0.13 technology CMOS device's performance
by: Leong, Vincent Kum Woh.
Published: (2008) -
Optimization of via patterns for 0.13 micrometer copper dual damascene technology using phase shift mask
by: Chen, Hao.
Published: (2008) -
Improved effective channel length extraction method for 0.09-0.13 mm CMOS
by: Eng, Chee Wee
Published: (2008) -
Computer-aided spice program for deep sub-micron devices
by: Yeo, Boon Hwang.
Published: (2008)