Copper nanowires bonding for three dimensional interconnections
Over the past few decades, the semiconductor industry has been advancing by increasing transistor density on a microchip through continuous device scaling based on the technology roadmap driven by Moore’s Law. However, new physical phenomena at scaled dimensions and fundamental limitations in materi...
Saved in:
Main Author: | Chun, Shu Rong |
---|---|
Other Authors: | Gan Chee Lip |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2016
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/69104 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Employment of a bi-layer of Ni(P)/Cu as a diffusion barrier in a Cu/Sn/Cu bonding structure for three-dimensional interconnects
by: Lee, Byunghoon, et al.
Published: (2013) -
Study of the evolution of Cu-Cu bonding interface imperfection under direct current stressing for three dimensional integrated circuits
by: Made, Riko I., et al.
Published: (2012) -
Effect of direct current stressing to Cu–Cu bond interface imperfection for three dimensional integrated circuits
by: Made, Riko I., et al.
Published: (2013) -
Electrical characterization and modeling on mechanical strength of copper to copper bonds for three dimensional integrated circuits
by: I Made Riko
Published: (2011) -
Controlled synthesis of copper nanowire
by: Ding, Xiang
Published: (2015)