Si nanowire CMOS transistors and circuits by top-down technology approach

Si nanowire CMOS transistors and circuits by top-down technology approach

10.1149/1.2911501

Saved in:

Bibliographic Details
Main Authors:	Balasubramanian, N., Singh, N., Rustogi, S.C., Buddharaju, K.D., Fu, J., Hui, Z., Balakumar, S., Agarwal, A., Manhas, S.K., Lo, G.Q., Kwong, D.L.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2016
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/130092
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	National University of Singapore

Similar Items

Chip-level thermoelectric power generators based on high-density silicon nanowire array prepared with top-down CMOS technology
by: Li, Y., et al.
Published: (2014)

Addressing performance bottlenecks for top-down engineered nanowire transistors
by: JIANG YU
Published: (2010)

Carbon nanowires fabrications via top down approach
by: Tan, Chong Wei, et al.
Published: (2013)

Top-down engineered silicon and germanium nanowire MOSFET
by: PENG JIANWEI
Published: (2011)

Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire contacts
by: Jiang, Y., et al.
Published: (2014)

Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory
by: Fu, J., et al.
Published: (2014)

Nanosphere lithography for ordered-arrayed semiconductor nanowire formation via top-down method
by: Low, Guorong.
Published: (2009)

Top-down Si nanowire technology in discrete charge storage nonvolatile memory application
by: FU JIA
Published: (2010)

Tripeptide-modified silicon nanowire based field-effect transistors as real-time copper ion sensors
by: Bi, X., et al.
Published: (2014)

Tripeptide-modified silicon nanowire based field-effect transistors as real-time copper ion sensors
by: Bi, X., et al.
Published: (2014)

Nickel-silicided Schottky junction CMOS transistors with gate-all-around nanowire channels
by: Tang, L. J., et al.
Published: (2012)

Metal-germanide Schottky Source/Drain transistor on Germanium substrate for future CMOS technology
by: Li, R., et al.
Published: (2014)

CMOS-compatible nanowire sensor arrays for detection of cellular bioelectricity
by: Chen, Peng, et al.
Published: (2012)

Nickel salicided source/drain extensions for performance improvement in ultrascaled (Sub 10 nm) Si-nanowire transistors
by: Jiang, Y., et al.
Published: (2014)

Transport characteristics of Si nanowires in bulk silicon and SOI wafers
by: Agarwal, A., et al.
Published: (2016)

Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors
by: Peng, J.W., et al.
Published: (2014)

Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
by: Singh, N., et al.
Published: (2014)

CMOS compatible Ge/Si core/shell nanowire gate-all-around pMOSFET integrated with HfO2/TaN gate stack
by: Peng, J.W., et al.
Published: (2014)

Silicon nanowires thermoelectric devices
by: Li, Y., et al.
Published: (2014)

Si-nanowire based gate-all-around nonvolatile SONOS memory cell
by: Fu, J., et al.
Published: (2014)

Uniaxially strained germanium-tin (GeSn) gate-all-around nanowire PFETs enabled by a novel top-down nanowire formation technology
by: Gong, X., et al.
Published: (2014)

New developments in Schottky source/drain high-k/metal gate CMOS transistors
by: Li, M.-F., et al.
Published: (2014)

Synaptic CMOS transistor
by: Chai, Zhen Hong
Published: (2020)

Tuning characteristics of the top-down attentional setting
by: Chua, F.K.
Published: (2014)

Online top-down shooter browser game.
by: Crisostomo, Aaron J., et al.
Published: (2012)

Strained silicon nanowire transistors with germanium source and drain stressors
by: Liow, T.-Y., et al.
Published: (2014)

Sub-femto-farad capacitance-voltage characteristics of single channel gate-all-around nano wire transistors for electrical characterization of carrier transport
by: Zhao, H., et al.
Published: (2014)

Silicon nanowire forthermoelectric applications: Effects of contact resistance
by: Li, Y., et al.
Published: (2014)

Nanowire FETs for Low Power CMOS Applications Featuring Novel Gate-All-Around Single Metal FUSI Gates with Dual φ m and v T Tune-ability
by: Jiang, Y., et al.
Published: (2014)

Adiabatic CMOS circuits
by: Tan, Whee Min.
Published: (2008)

Temperature dependence of carrier transport of a silicon nanowire schottky-barrier field-effect transistor
by: Yang, W.F., et al.
Published: (2014)

A CMOS ISFET interface circuit with dynamic current temperature compensation technique
by: Chan, Pak Kwong, et al.
Published: (2009)

Germanium source and drain stressors for ultrathin-body and nanowire field-effect transistors
by: Liow, T.-Y., et al.
Published: (2014)

Remarks on the difficulty of top-down supervisor synthesis
by: Lin, Liyong., et al.
Published: (2013)

Top-down community building and the politics of inclusion
by: Wekker , Fenneke
Published: (2020)

An enabling device technology for future superjunction power integrated circuits
by: Chen, Y., et al.
Published: (2014)

Modeling of stress-retarded orientation-dependent oxidation: Shape engineering of silicon nanowire channels
by: Ma, F.-J., et al.
Published: (2014)

Dual-rail CMOS circuits
by: Zhang, Beixi
Published: (2016)

Self-timed CMOS circuits
by: Lakshminarayanan Srinivasan
Published: (2008)

Low power CMOS circuits
by: Teo, Kok Chin
Published: (2014)