A low-power Low-VDD nonvolatile latch using spin transfer torque MRAM

A low-power Low-VDD nonvolatile latch using spin transfer torque MRAM

10.1109/TNANO.2013.2280338

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書目詳細資料
Main Authors:	Huang, K., Lian, Y.
其他作者:	ELECTRICAL & COMPUTER ENGINEERING
格式:	Article
出版:	2014
主題:	Low power Nonvolatile flip-flop (nvFF) Nonvolatile latch (nvLatch) Nonvolatile memory (NVM) Spin-torque transfer MRAM (STT-MRAM) Two-phase write approach
在線閱讀:	http://scholarbank.nus.edu.sg/handle/10635/54321
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	National University of Singapore

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