Design of high-speed low-power clock and data recovery circuit

Design of high-speed low-power clock and data recovery circuit

In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.

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書目詳細資料
主要作者:	Alper, Cabuk
其他作者:	Yeo, Kiat Seng
格式:	Theses and Dissertations
出版:	2008
主題:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
在線閱讀:	https://hdl.handle.net/10356/4801
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	Nanyang Technological University

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