Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit

Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit

In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm will leads to a longer lock time for phase tracking loop and small ppm will lead...

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書目詳細資料
Main Authors:	Tan, Yung Sern, Yeo, Kiat Seng, Boon, Chirn Chye, Do, Manh Anh
其他作者:	School of Electrical and Electronic Engineering
格式:	Conference or Workshop Item
語言:	English
出版:	2013
主題:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
在線閱讀:	https://hdl.handle.net/10356/99816 http://hdl.handle.net/10220/17712
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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