Bed of nails(B0N) - 100 microns pitch wafer level off-chip interconnects for microelectronic packaging applications
Master's
Saved in:
Main Author: | VEMPATI SRINIVASARAO |
---|---|
Other Authors: | MECHANICAL ENGINEERING |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2010
|
Subjects: | |
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/15010 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Language: | English |
Similar Items
-
Test bench modeling and characterization for fine pitch wafer level packaged devices
by: Jayabalan, J., et al.
Published: (2014) -
Compliant Chip-to-Package Interconnects for Wafer Level Packaging
by: LIAO EBIN
Published: (2011) -
Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging
by: Liao, E.B., et al.
Published: (2014) -
Development of stretch solder interconnections for wafer level packaging
by: Rajoo, R., et al.
Published: (2014) -
Fatigue and bridging study of high-aspect-ratio multicopper-column flip-chip interconnects through solder joint shape modeling
by: Liao, E.B., et al.
Published: (2014)