Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)

• المؤلف الرئيسي: Low, Hong Guan.
• مؤلفون آخرون: Koh, Liang Mong
• التنسيق: Theses and Dissertations
• منشور في: 2008
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/4811
• المؤسسة: Nanyang Technological University

This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional...