Electromigration study of through silicon via (TSV)
In the continuous drive for smaller chips (Moore’s Law) and heterogeneous semiconductor applications, traditional processing and packaging technologies may not be able to support this trend. 3-D IC can offer a greater packing density in the same footprint as 2-D miniaturizing is reaching its physic...
Saved in:
Main Author: | Tan, Yeow Chong |
---|---|
Other Authors: | Tan Cher Ming |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2011
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/43544 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Through-silicon-via (TSV) design, fabrication and characterization for 3D IC applications
by: Zhang, Lin
Published: (2014) -
Dielectric quality of 3D capacitor embedded in through-silicon via (TSV)
by: Lin, Ye, et al.
Published: (2020) -
Leakage current conduction mechanism in 3D capacitor embedded in Through-Silicon Via (TSV)
by: Lin, Ye, et al.
Published: (2020) -
Design and building of solder and TSV daisy chain electromigration tester
by: Ser, Edwin Wei Jun.
Published: (2011) -
Electrical characteristics of three-dimensional metal-insulator-metal (3-D MIM) capacitor embedded in partially-filled Through-Silicon Via (TSV)
by: Lin, Ye, et al.
Published: (2020)