Electromigration study of through silicon via (TSV)
In the continuous drive for smaller chips (Moore’s Law) and heterogeneous semiconductor applications, traditional processing and packaging technologies may not be able to support this trend. 3-D IC can offer a greater packing density in the same footprint as 2-D miniaturizing is reaching its physic...
Saved in:
主要作者: | Tan, Yeow Chong |
---|---|
其他作者: | Tan Cher Ming |
格式: | Theses and Dissertations |
語言: | English |
出版: |
2011
|
主題: | |
在線閱讀: | https://hdl.handle.net/10356/43544 |
標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
相似書籍
-
Through-silicon-via (TSV) design, fabrication and characterization for 3D IC applications
由: Zhang, Lin
出版: (2014) -
Dielectric quality of 3D capacitor embedded in through-silicon via (TSV)
由: Lin, Ye, et al.
出版: (2020) -
Leakage current conduction mechanism in 3D capacitor embedded in Through-Silicon Via (TSV)
由: Lin, Ye, et al.
出版: (2020) -
Design and building of solder and TSV daisy chain electromigration tester
由: Ser, Edwin Wei Jun.
出版: (2011) -
Electrical characteristics of three-dimensional metal-insulator-metal (3-D MIM) capacitor embedded in partially-filled Through-Silicon Via (TSV)
由: Lin, Ye, et al.
出版: (2020)