Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging
10.1016/j.chemosphere.2006.02.010
Saved in:
Main Authors: | Liao, E.B., Tay, A.A.O., Ang, S.S., Feng, H.H., Nagarajan, R., Kripesh, V. |
---|---|
Other Authors: | MECHANICAL ENGINEERING |
Format: | Article |
Published: |
2014
|
Subjects: | |
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/60918 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Fatigue and bridging study of high-aspect-ratio multicopper-column flip-chip interconnects through solder joint shape modeling
by: Liao, E.B., et al.
Published: (2014) -
Bed of nails(B0N) - 100 microns pitch wafer level off-chip interconnects for microelectronic packaging applications
by: VEMPATI SRINIVASARAO
Published: (2010) -
Compliant Chip-to-Package Interconnects for Wafer Level Packaging
by: LIAO EBIN
Published: (2011) -
Planar microspring - A novel compliant chip-to-package interconnect for wafer-level packaging
by: Liao, E.B., et al.
Published: (2014) -
Development of stretch solder interconnections for wafer level packaging
by: Rajoo, R., et al.
Published: (2014)