Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium source
10.1143/JJAP.47.2593
Saved in:
Main Authors: | Toh, E.-H., Wang, G.H., Chan, L., Sylvester, D., Heng, C.-H., Samudra, G.S., Yeo, Y.-C. |
---|---|
Other Authors: | ELECTRICAL & COMPUTER ENGINEERING |
Format: | Article |
Published: |
2014
|
Subjects: | |
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/55624 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Tunneling field-effect transistor: Effect of strain and temperature on tunneling current
by: Guo, P.-F., et al.
Published: (2014) -
I-MOS transistor with an elevated silicon-germanium impact-ionization region for bandgap engineering
by: Toh, E.-H., et al.
Published: (2014) -
Tunneling Field-Effect Transistors for Low Power Logic: Design, Simulation and Technology Demonstration
by: YANG YUE
Published: (2013) -
Strain and materials engineering for the I-MOS transistor with an elevated impact-ionization region
by: Toh, E.-H., et al.
Published: (2014) -
Advanced Transistors for Supply Voltage Reduction: Tunneling Field-Effect Transistors and High-Mobility MOSFETS
by: GUO PENGFEI
Published: (2013)