Investigation of interconnect layout on CU/Low-K TDDB reliability

• المؤلف الرئيسي: Ong, Ran Xing
• مؤلفون آخرون: Gan Chee Lip
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2015
• الموضوعات: DRNTU::Engineering::Materials::Microelectronics and semiconductor materials
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/62521
• المؤسسة: Nanyang Technological University

Traditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on T...