Investigation of interconnect layout on CU/Low-K TDDB reliability

Investigation of interconnect layout on CU/Low-K TDDB reliability

Traditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on T...

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書目詳細資料
主要作者:	Ong, Ran Xing
其他作者:	Gan Chee Lip
格式:	Theses and Dissertations
語言:	English
出版:	2015
主題:	DRNTU::Engineering::Materials::Microelectronics and semiconductor materials
在線閱讀:	https://hdl.handle.net/10356/62521
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	Nanyang Technological University
語言:	English

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